1. Field of the Invention
This invention has as its object a sample and hold circuit for a liquid crystal display screen.
2. Discussion of the Background
A liquid crystal display screen is generally in the form illustrated in FIG. 1. The screen itself, ECR, consists of addressing lines L and columns C, of a matrix of pixels P, each connected to a transistor TFT whose state is controlled by an associated line L and column C.
Such a screen is controlled by a line control circuit CCL, which sequentially applies an addressing voltage (for example, several volts) to the lines, and by a column control circuit CCC, which applies to all the columns voltages reflecting the light intensity of the points to be displayed on the addressed line. The overall image is thus displayed line by line.
Column control circuit CCC receives a video signal SV delivered by a video circuit CV. This signal generally consists of three components corresponding to the three primary components of a color image.
If screen ECR has 162 columns, circuit CCC comprises 162 elementary column control circuits, placed in parallel, and 162 outputs connected to various columns. Each elementary column control circuit (also called "driver column" in the technical literature) comprises a sample and hold circuit whose function is to sample the video signal at a given moment corresponding to the column to be controlled and to hold this sample on the column for the entire addressing period of a line ("sample and hold" function in English terminology).
This invention relates to such a sample and hold circuit.
The production of a sample and hold circuit for a liquid crystal display screen poses many problems.
First of all, it should allow the sampling of the video signal relative to a line while the signals relative to the preceding line are applied on the columns.
Further, if it is desired to be able to supply a large-sized display screen having a high number of columns (more than a hundred), a circuit of very low electrical consumption and exhibiting a short loading period for a high capacitive load is required.
Finally, it is desirable that the structure of the circuit makes it possible to compensate the offset voltages caused by the amplification and the shaping of the video signals.
The sample and hold circuits of the prior art present all the drawbacks. Thus, in the circuit marketed by the HITACHI Company under reference HD 66300T, for example, four sample and hold circuits per column, working alternately, are used. The circuit thus contains 480 sample and hold circuits for a 120 column screen. The electrical consumption is therefore very great. Further, in such a structure, it is not possible to correct the offset voltage.
Display screen control circuits comprising a first sampling stage consisting of a sampling capacitor and a second stage comprising a holding capacitor are known by documents EP-A-0 381 429 and GB-2 146 479. In this type of circuit, it is necessary to transfer the load of the first capacitor to the second and the output signal consists of the voltage present at the terminals of the second capacitor. To avoid degrading the signal, a first (sampling) capacitor with a much larger capacitance than that of the second (holding) capacitor is necessary. The loading time of the first capacitor is increased however, due to its relatively large size. Further, since the output voltage is linked to the input voltage by a ratio C1/C1+C2 (where C1 and C2 are the capacitances of the first and second capacitors), at best, the output voltage is equal to the input voltage. Further, the large value of the first capacitor leads to an excessive bulkiness and seriously limits the integration possibilities of the circuit. Finally, the load impedance of the video amplifiers is considerably increased.
Further, another solution which avoids the use of a holding capacitor (cf. FIG. 11 of this document) is known by document FR-A-2 458 117. This solution consists in using two identical sampling paths mounted in parallel and working alternately. However, in this solution, the gain of the circuit is limited to 1 and doubling of the number of paths naturally increases the bulkiness of the circuit.